Chip Design of the Switched-Capacitor Second-Order Delta-Sigma Modulator

• Main Authors: Yu-Hao Lai, 賴昱豪
• Other Authors: 宋國明
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/hv39ab

碩士 === 國立臺北科技大學 === 通訊與資訊產業研發碩士專班 === 96 === This paper presents a design process of the switched-capacitor delta-sigma modulator, for audio system. In this system, the over-sampling technique is widely used to implement the interface between the analog and the digital signals in VLSI systems. The destination is to enhance the accuracy of the modulator up to 16-20 bits with 20 kHz bandwidth. That is, the sigma delta modulator not only works with perfect accuracy, but also meets the specification without further effort. In this thesis, the basic principle of sigma-delta modulator and the design flow chart from simulation to implement will be presented. Furthermore, the modulator will be implemented in TSMC 0.35 μm CMOS process. The simulated results show that the maximum signal-to-noise and distortion ratio (SNDR) is 86 dB, and the power dissipation is 5.66 mW with the sampling rate of 5.12 MHz and the oversampling ratio of 128.