| Summary: | 碩士 === 國立臺北科技大學 === 電機工程系所 === 96 === This thesis presents the design and implementation of a 1.8 V, 100 MHz CMOS digital transmitter. The digital transmitter consists of a 10-bit 100 MHz digital-to-analog converter (DAC), a low-pass filter, and a fully differential current-mode line-driver, which has been fabricated with the TSMC 0.18 μm 1P6M CMOS technology.
To increase the operating speed, the design digital-to-analog converter is based on the current-switch mode. Furthermore, we use a new current-source biasing technique to reduce the current error caused by inevitable threshold-voltage variation. It deserves noticing that the digital-to-analog converter consists of 8-bit thermometer-encoding and 2-bit binary-encoding. The goal is to achieve smaller layout area, to reduce the complexity of digital circuit, and to decrease the differential nonlinearity error (DNL).
For the design of line driver, this thesis focuses on the impedance-matching scheme and low-voltage architecture to achieve high power efficiency. The utilization of impedance synthesis is to eliminate the matching resistor which works with extra power consumption. A low-voltage class-AB output structure is also demonstrated. Furthermore, the capacitive feedforward path is used to reduce the crossover distortion and the current-feedback circuit is added to line driver to increase linearity. The simulated results show that the output voltage swing of the line driver is 2 VPP. Over a 100 Ω differential load, and the THD is -48 dB with the operating frequency of 100 MHz at 1.8 V power supply.
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