Novel Low Power SRAM Cell and Peripheral Circuit Design

碩士 === 南台科技大學 === 電子工程系 === 96 === The development of VLSI design nowadays is mainly focused on low power consumption. With the evolution of CMOS process, device sizes and power supply are also improved. The transistor counts within a chip system is increasing due to huge demand of memory size. In t...

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Main Authors:	De-Yun Li, 李德耘
Other Authors:	Po-Ming Li
Format:	Others
Language:	zh-TW
Published:	2008
Online Access:	http://ndltd.ncl.edu.tw/handle/14817404101542345194

id	ndltd-TW-096STUT0428046
record_format	oai_dc
spelling	ndltd-TW-096STUT04280462016-11-22T04:12:08Z http://ndltd.ncl.edu.tw/handle/14817404101542345194 Novel Low Power SRAM Cell and Peripheral Circuit Design 新式的靜態隨機存取記憶體單元與周邊電路設計 De-Yun Li 李德耘碩士南台科技大學電子工程系 96 The development of VLSI design nowadays is mainly focused on low power consumption. With the evolution of CMOS process, device sizes and power supply are also improved. The transistor counts within a chip system is increasing due to huge demand of memory size. In this paper, we try to study memories which occupied a lot of layout area. The decreasing of device sizes introduces many unpredictable problems such as static power dissipation. Thus, we propose 3 static random access memory architectures with the advantages of low dynamic/static power dissipation. The proposed designs does prove its improvements after we compete with prior design. As to chip read/write operation, the power consumption in charge/discharge operation of bit line during read/write period is also crucial. We've add selectable charge bit line design and refine the corrosponding circuits. In addition, we also propose a novel design of address sense circuit which also improves in power consumption and transistor counts. Po-Ming Li 李博明 2008 學位論文 ; thesis 69 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 南台科技大學 === 電子工程系 === 96 === The development of VLSI design nowadays is mainly focused on low power consumption. With the evolution of CMOS process, device sizes and power supply are also improved. The transistor counts within a chip system is increasing due to huge demand of memory size. In this paper, we try to study memories which occupied a lot of layout area. The decreasing of device sizes introduces many unpredictable problems such as static power dissipation. Thus, we propose 3 static random access memory architectures with the advantages of low dynamic/static power dissipation. The proposed designs does prove its improvements after we compete with prior design. As to chip read/write operation, the power consumption in charge/discharge operation of bit line during read/write period is also crucial. We've add selectable charge bit line design and refine the corrosponding circuits. In addition, we also propose a novel design of address sense circuit which also improves in power consumption and transistor counts.
author2	Po-Ming Li
author_facet	Po-Ming Li De-Yun Li 李德耘
author	De-Yun Li 李德耘
spellingShingle	De-Yun Li 李德耘 Novel Low Power SRAM Cell and Peripheral Circuit Design
author_sort	De-Yun Li
title	Novel Low Power SRAM Cell and Peripheral Circuit Design
title_short	Novel Low Power SRAM Cell and Peripheral Circuit Design
title_full	Novel Low Power SRAM Cell and Peripheral Circuit Design
title_fullStr	Novel Low Power SRAM Cell and Peripheral Circuit Design
title_full_unstemmed	Novel Low Power SRAM Cell and Peripheral Circuit Design
title_sort	novel low power sram cell and peripheral circuit design
publishDate	2008
url	http://ndltd.ncl.edu.tw/handle/14817404101542345194
work_keys_str_mv	AT deyunli novellowpowersramcellandperipheralcircuitdesign AT lǐdéyún novellowpowersramcellandperipheralcircuitdesign AT deyunli xīnshìdejìngtàisuíjīcúnqǔjìyìtǐdānyuányǔzhōubiāndiànlùshèjì AT lǐdéyún xīnshìdejìngtàisuíjīcúnqǔjìyìtǐdānyuányǔzhōubiāndiànlùshèjì
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Novel Low Power SRAM Cell and Peripheral Circuit Design

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