A Study of GFP Frame Delineation Optimization Based on FPGA
碩士 === 國立臺灣科技大學 === 電機工程系 === 96 === This thesis presents a new optimization approach for GFP (Generic Framing Procedure) frame delineation on an FPGA (Field-Programmable Gate Array). The using of FPGA characteristic of module enables the hardware circuit to share and easy to develop. Our approach n...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/18934976357089342240 |
| Summary: | 碩士 === 國立臺灣科技大學 === 電機工程系 === 96 === This thesis presents a new optimization approach for GFP (Generic Framing Procedure) frame delineation on an FPGA (Field-Programmable Gate Array). The using of FPGA characteristic of module enables the hardware circuit to share and easy to develop. Our approach not only can minimize logic gates of FPGA to save the volume and cost, but also performs 64-bit data size computation and comparison of CRC-16 on a single clock cycle. The proposed technique can improve the efficiency of the traditional methods that take more than one clock cycle to perform GFP frame delineation.
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