1V 0.18um CMOS 5.8GHz RF Front-End Receiver Chip Design for DSRC Application

碩士 === 國立臺灣科技大學 === 電子工程系 === 96 === This thesis describe a 1 voltage 0.18um CMOS 5.8GHz RF front-end for DSRC (Dedicated Short Range Communication) application. This circuit integrated a single-ended low noise amplifier (LNA), a single-ended RF input, differential IF output, Gilbert Cell types mixe...

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Bibliographic Details
Main Authors:	Han-chien Hsun, 韓建勳
Other Authors:	Jhin-Fang Huang
Format:	Others
Language:	en_US
Published:	2008
Online Access:	http://ndltd.ncl.edu.tw/handle/86647838658441816792

id	ndltd-TW-096NTUS5428138
record_format	oai_dc
spelling	ndltd-TW-096NTUS54281382016-05-13T04:15:16Z http://ndltd.ncl.edu.tw/handle/86647838658441816792 1V 0.18um CMOS 5.8GHz RF Front-End Receiver Chip Design for DSRC Application 應用於DSRC系統1伏0.18umCMOS5.8GHz射頻接收機前端電路晶片設計 Han-chien Hsun 韓建勳碩士國立臺灣科技大學電子工程系 96 This thesis describe a 1 voltage 0.18um CMOS 5.8GHz RF front-end for DSRC (Dedicated Short Range Communication) application. This circuit integrated a single-ended low noise amplifier (LNA), a single-ended RF input, differential IF output, Gilbert Cell types mixer, and a LC-tank voltage controlled oscillator (VCO). The receiver has been using the standard TSMC 0.18um 1P6M RF CMOS process, design a 5.8GHz RF front-end receiver chip for DSRC application. The integrated RF receiver chip has 24.9dB conversion gain, noise figure is 3.43dB. The 1dB compression point is -14.1dBm. The third-order intercept point (IIP3) is -6.36dBm. The total power consumption is 17.6mW from 1V power supply. The integrated RF front end receiver chip area is 0.817*1.244 mm2. Jhin-Fang Huang Ron-Yi Liu 黃進芳劉榮宜 2008 學位論文 ; thesis 95 en_US
collection	NDLTD
language	en_US
format	Others
sources	NDLTD
description	碩士 === 國立臺灣科技大學 === 電子工程系 === 96 === This thesis describe a 1 voltage 0.18um CMOS 5.8GHz RF front-end for DSRC (Dedicated Short Range Communication) application. This circuit integrated a single-ended low noise amplifier (LNA), a single-ended RF input, differential IF output, Gilbert Cell types mixer, and a LC-tank voltage controlled oscillator (VCO). The receiver has been using the standard TSMC 0.18um 1P6M RF CMOS process, design a 5.8GHz RF front-end receiver chip for DSRC application. The integrated RF receiver chip has 24.9dB conversion gain, noise figure is 3.43dB. The 1dB compression point is -14.1dBm. The third-order intercept point (IIP3) is -6.36dBm. The total power consumption is 17.6mW from 1V power supply. The integrated RF front end receiver chip area is 0.817*1.244 mm2.
author2	Jhin-Fang Huang
author_facet	Jhin-Fang Huang Han-chien Hsun 韓建勳
author	Han-chien Hsun 韓建勳
spellingShingle	Han-chien Hsun 韓建勳 1V 0.18um CMOS 5.8GHz RF Front-End Receiver Chip Design for DSRC Application
author_sort	Han-chien Hsun
title	1V 0.18um CMOS 5.8GHz RF Front-End Receiver Chip Design for DSRC Application
title_short	1V 0.18um CMOS 5.8GHz RF Front-End Receiver Chip Design for DSRC Application
title_full	1V 0.18um CMOS 5.8GHz RF Front-End Receiver Chip Design for DSRC Application
title_fullStr	1V 0.18um CMOS 5.8GHz RF Front-End Receiver Chip Design for DSRC Application
title_full_unstemmed	1V 0.18um CMOS 5.8GHz RF Front-End Receiver Chip Design for DSRC Application
title_sort	1v 0.18um cmos 5.8ghz rf front-end receiver chip design for dsrc application
publishDate	2008
url	http://ndltd.ncl.edu.tw/handle/86647838658441816792
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1V 0.18um CMOS 5.8GHz RF Front-End Receiver Chip Design for DSRC Application

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