Synthesis and Design of Parameter Extractors for Low-Power Pre-computation-Based Content-Addressable Memory

碩士 === 國立臺灣科技大學 === 電子工程系 === 96 === Content addressable memory (CAM) is frequently used in many applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due to its ability to improve application performance by using parallel comparison...

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Main Authors: Jui-Yuan Hsieh, 謝瑞遠
Other Authors: Shanq-Jang Ruan
Format: Others
Language:en_US
Published: 2008
Online Access:http://ndltd.ncl.edu.tw/handle/49829928186340404120
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spelling ndltd-TW-096NTUS54281222016-05-13T04:15:16Z http://ndltd.ncl.edu.tw/handle/49829928186340404120 Synthesis and Design of Parameter Extractors for Low-Power Pre-computation-Based Content-Addressable Memory 用於低功率預先計算內容可定址記憶體中特徵值擷取器之合成與設計 Jui-Yuan Hsieh 謝瑞遠 碩士 國立臺灣科技大學 電子工程系 96 Content addressable memory (CAM) is frequently used in many applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due to its ability to improve application performance by using parallel comparison to reduce search time. Although the use of parallel comparison results in fast search time, it also significantly increases power consumption. In this master thesis, a gate-block selection algorithm is presented. The proposed algorithm can synthesize a proper parameter extractor of the pre-computation-based content-addressable memory (PB-CAM) to enhance power efficiency for specific applications. Furthermore, a novel CAM cell design with single bit-line is proposed. The proposed CAM cell design requires only one heavy loading bit-line and merely is constructed with eight transistors. The whole PB-CAM design was described in Spice in TSMC 0.35μm double-poly quadruple-metal CMOS process. We used Synopsys Nanosim to estimate power consumption. With a 128 words by 32 bits CAM size, the experimental results showed that our proposed PB-CAM effectively reduces 8.99% to 27.42% of comparison operations in the CAM and saves 8.65% to 24.84% in power reduction by synthesizing a proper parameter extractor of the PB-CAM compared with the 1’s count PB-CAM. As a result, it implies that our proposed PB-CAM is more flexible and adaptive for specific applications such as embedded systems. The major contribution of this master thesis is that it presents a gate-block selection algorithm to synthesize a proper parameter extractor of the PB-CAM for a specific data type and proposes a novel CAM cell design to improve the deficiency of the specific CAM cell design proposed in the 1’s count PB-CAM. Shanq-Jang Ruan 阮聖彰 2008 學位論文 ; thesis 55 en_US
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description 碩士 === 國立臺灣科技大學 === 電子工程系 === 96 === Content addressable memory (CAM) is frequently used in many applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due to its ability to improve application performance by using parallel comparison to reduce search time. Although the use of parallel comparison results in fast search time, it also significantly increases power consumption. In this master thesis, a gate-block selection algorithm is presented. The proposed algorithm can synthesize a proper parameter extractor of the pre-computation-based content-addressable memory (PB-CAM) to enhance power efficiency for specific applications. Furthermore, a novel CAM cell design with single bit-line is proposed. The proposed CAM cell design requires only one heavy loading bit-line and merely is constructed with eight transistors. The whole PB-CAM design was described in Spice in TSMC 0.35μm double-poly quadruple-metal CMOS process. We used Synopsys Nanosim to estimate power consumption. With a 128 words by 32 bits CAM size, the experimental results showed that our proposed PB-CAM effectively reduces 8.99% to 27.42% of comparison operations in the CAM and saves 8.65% to 24.84% in power reduction by synthesizing a proper parameter extractor of the PB-CAM compared with the 1’s count PB-CAM. As a result, it implies that our proposed PB-CAM is more flexible and adaptive for specific applications such as embedded systems. The major contribution of this master thesis is that it presents a gate-block selection algorithm to synthesize a proper parameter extractor of the PB-CAM for a specific data type and proposes a novel CAM cell design to improve the deficiency of the specific CAM cell design proposed in the 1’s count PB-CAM.
author2 Shanq-Jang Ruan
author_facet Shanq-Jang Ruan
Jui-Yuan Hsieh
謝瑞遠
author Jui-Yuan Hsieh
謝瑞遠
spellingShingle Jui-Yuan Hsieh
謝瑞遠
Synthesis and Design of Parameter Extractors for Low-Power Pre-computation-Based Content-Addressable Memory
author_sort Jui-Yuan Hsieh
title Synthesis and Design of Parameter Extractors for Low-Power Pre-computation-Based Content-Addressable Memory
title_short Synthesis and Design of Parameter Extractors for Low-Power Pre-computation-Based Content-Addressable Memory
title_full Synthesis and Design of Parameter Extractors for Low-Power Pre-computation-Based Content-Addressable Memory
title_fullStr Synthesis and Design of Parameter Extractors for Low-Power Pre-computation-Based Content-Addressable Memory
title_full_unstemmed Synthesis and Design of Parameter Extractors for Low-Power Pre-computation-Based Content-Addressable Memory
title_sort synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory
publishDate 2008
url http://ndltd.ncl.edu.tw/handle/49829928186340404120
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