| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 96 === Content addressable memory (CAM) is frequently used in many applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due to its ability to improve application performance by using parallel comparison to reduce search time. Although the use of parallel comparison results in fast search time, it also significantly increases power consumption.
In this master thesis, a gate-block selection algorithm is presented. The proposed algorithm can synthesize a proper parameter extractor of the pre-computation-based content-addressable memory (PB-CAM) to enhance power efficiency for specific applications. Furthermore, a novel CAM cell design with single bit-line is proposed. The proposed CAM cell design requires only one heavy loading bit-line and merely is constructed with eight transistors.
The whole PB-CAM design was described in Spice in TSMC 0.35μm double-poly quadruple-metal CMOS process. We used Synopsys Nanosim to estimate power consumption. With a 128 words by 32 bits CAM size, the experimental results showed that our proposed PB-CAM effectively reduces 8.99% to 27.42% of comparison operations in the CAM and saves 8.65% to 24.84% in power reduction by synthesizing a proper parameter extractor of the PB-CAM compared with the 1’s count PB-CAM. As a result, it implies that our proposed PB-CAM is more flexible and adaptive for specific applications such as embedded systems.
The major contribution of this master thesis is that it presents a gate-block selection algorithm to synthesize a proper parameter extractor of the PB-CAM for a specific data type and proposes a novel CAM cell design to improve the deficiency of the specific CAM cell design proposed in the 1’s count PB-CAM.
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