| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 96 === Chapter 4 in this thesis presents a new divide-by-2 and -4 injection-locked frequency divider (ILFD). The ILFD consists of a new 3.5 GHz quadrature voltage controlled oscillator (QVCO) and two NMOS switches, which are in parallel with the QVCO resonators for signal injection. The proposed CMOS ILFD has been implemented with the TSMC 0.18-μm CMOS technology and the core power consumption is 10.95 mW at the supply voltage of 1.5 V. The free-running frequency of the QILFD is tunable from 3.02 GHz to 3.53 GHz. At the input power of 0 dBm, the total divide-by-2 locking range is from 5.96 GHz to 7.68 GHz as the tuning voltage is varied from 0 V to 1.5 V. The phase noise of the locked output spectrum is lower than that of free running ILFD in the 2 mode. The phase deviation of quadrature output is about 0.14o .
Chapter 5 presents a new technique for designing multi-phase VCOs, which were implemented in the standard TSMC 0.35 μm SiGe 3P3M BiCMOS process. The quadrature voltage-controlled oscillator (QVCO) consists of two direct- injection locked frequency dividers (ILFDs) with a tail MOSFET. The 2nd harmonic frequency component at the drain node of tail transistor in one ILFD is injected to the gate of injection MOSFET in the other ILFD to couple the two independent ILFDs. The eight- phase VCO is also designed with similar technique to couple four differential VCOs. At the supply voltage of 3.0 V, the output phase noise of the QVCO is -118.22 dBc/Hz at 1MHz offset frequency from the carrier frequency of 2.28 GHz, and the figure of merit is -173.25 dBc/Hz. At the supply voltage of 3.0 V, the total power consumption is 14.4 mW. At the supply voltage of 3.0 V, the output phase noise of the eight-phase VCO is -116.14 dBc/Hz at 1MHz offset frequency from the carrier frequency of 2.92 GHz, and the figure of merit is -171.3 dBc/Hz.
Chapter 6 presents an integrated VCO injection-locked frequency divider (ILFD) circuit. The divide-by-4 injection locked frequency divider consists of a 2.8GHz nMOS-core VCO with a direct-injection MOSFET and the VCO is a 5.6GHz cross-coupled p-core CMOS VCO. The ILFD divides down the injection signal frequency by 4, while the VCO outputs a second harmonic using the tail inductor, and the harmonic is applied to the gate of injection in the ILFD. The ILFD outputs a signal with half of the fundamental frequency while the VCO outputs a signal with the fundamental frequency. The circuit is implemented in a standard 0.18-μm CMOS process. At the supply voltage of 1.5V, the ILFD can be tunable from 2.772GHZ to 2.928GHZ with a corresponding VCO frequency from 5.529GHZ~5.848GHZ.
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