| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 96 === This thesis mainly presents two circuit used the transformer coupling technique. A 5.6GHz low power balanced voltage-controlled oscillator (VCO) is designed and implemented in a 0.18 μm CMOS 1P6M process. The designed circuit topology consists of two single-ended complementary Colpitts LC-tank VCOs configured in a balanced topology. At the supply voltage of 1.2 V, the output phase noise of the VCO is -119.13dBc/Hz at 1MHz offset frequency from the carrier frequency of 5.6 GHz, and the figure of merit is -190.29dBc/Hz. Total VCO core power consumption is 2.4 mW. Tuning range is about 600 MHz, from 5.36 to 5.96 GHz, while the control voltage was tuned from 0 V to 1.2 V.
A low-power injection locked frequency divider (ILFD) based on the all-NMOS Hartley VCO topology. The ILFD uses 3-D transformer to form the resonator and save chip area. At the supply voltage of 1.2 V, the tuning range of the free running ILFD is from 2.32 GHz to 2.65 GHz, about 330 MHz while the tuning voltage is tuned from 0 to 1.8 V. At the injection signal power of 0dBm, the total locking range of the ILFD in the divide-by-2 mode is from 4.39 to 5.83 GHz, about 1.44 GHz. The total locking range of the ILFD in the 4 mode is from 9.18 to 10.4 GHz, about 1.22 GHz. The ILFD dissipates 3.42 mW at the supply voltage of 1.2 V and was fabricated in the 1P6M 0.18 μm CMOS process. The phase noise of the locked ILFD tracks with the low-phase-noise injection source.
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