The Design and Verification of an ARM v4 Instruction Set Architecture Compatible Memory-Management-Unit IP

• Main Authors: Chung-yang Hsu, 徐昌陽
• Other Authors: M.B. Lin
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/60592735992821194446

碩士 === 國立臺灣科技大學 === 電子工程系 === 96 === MMU, sometimes called “paged memory management unit”（PMMU）, is a computer hardware component responsible for handling accesses to memory requested by CPU. Its functions include address translation, access permission checks for instruction and data address, and memory sharing. By translating virtual addresses to physical address, it helps the operating system manage virtual memory with hardware support. In this thesis, an MMU IP （Intellectual Property） compatible to ARM v4 architecture is proposed. The MMU consists of an FSM（Finite State Machine） Control Unit, TLB（Translation Look-aside Buffer）, a calculation and protection module, and an AMBA（Advanced Microcontroller Bus Architecture） Interface to read the translation table in the main memory. Proto-ARM922, which is combined proto-ARM9M with cache, system co-processor, MMU, and AMBA interface, has been implemented and verified with Xilinx Spartan-3 XC3S1500-4FG676 FPGA and TSMC 0.18 μm cell library. In the FPGA part, it takes 21211 LUTs and operates at the maximum working frequency of 11 MHz. Furthermore, all of the testing programs are run successfully in FPGA development board. In the cell-based part, the core occupies 3183.26 μm × 3423.08 μm, which is approximately equivalent to 481533 gates, and the whole chip occupies 4088 μm × 4081 μm, and in the SS （Slow NMOS Slow PMOS model） simulation condition it operates at the maximum working frequency of 40 MHz, and it comsumes about 167.1 mW.