Power line communication sensor network receiver

• Main Authors: Shun-Yang Ko, 柯舜揚
• Other Authors: Shey-Shi Lu
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/32655760970963286416

碩士 === 國立臺灣大學 === 電機工程學研究所 === 96 === This thesis presents the design and implements of the Power line communication receiver adapted to CENCLEC BS EN 50065-1 standard in TSMC 0.35 2P4M CMOS process. The main function, lowpass filter, is verified by two chips. One is the 3rd-order chebyshev LowPass filter. The filter type of the 3rd-order chebyshev LowPass filter is a leapfrog structure, and cascade method is applied to implement this high-order filter. According to measurement results, the gain level of the filter is 0dB. The f-3dB is 2.28MHz. The die area is 1.086 x 0.947 mm2 and the power consumption is 8.413mW. The other chip is designed for power line communication receiver which is comprised of an AGC circuit, a thirteenth-order Butterworth LowPass filter, an Equalizer, a peak detector, and a comparator. The f-3dB of the thirteenth-order Butterworth LowPass filter realized by Sallen-Key Biquad cascade is 125K Hz. The die area is 1.914 x 1.853 mm2 and the power consumption is 21.21mW.