Simulation Study of Bulk FinFET and Ge Quantum Well pFET

• Main Authors: Hung-Chih Chang, 張弘志
• Other Authors: Chee-Wee Liu
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/81706112428487610698

碩士 === 國立臺灣大學 === 電機工程學研究所 === 96 === Bulk FinFET has advantages of heat dissipation, wafer cost, process compatibility and extendibility of conventional planar MOSFET technologies. The combination of recess channel array transistors (RCAT) technology and triple-gate in bulk silicon prove excellent SCEs control ability. It owns superior subthreshold slope (~70 mV/dec) and DIBL characteristics in simulation works. Due to the fully depleted fin channel, the subthrehold voltage is modified by not only channel doping but also the fin width and fin height. The saddle-like FinFET structure shows good immunity of electric characteristics of recess depth variation and reverse body bias comparing to RCAT structure. To integrate with DRAMs process, the leakage current must be suppressed. With higher channel doping, it reduces the Ioff current and subthreshold slope. By adopting LDD in S/D region, the band-to-band-tunneling generation is smaller. Also, increasing the thickness of gate-to-drain oxide, can help the leakage suppression a lot but only a slightly control ability sacrifice. A Si-cap/Ge/Si pFET structure based on 90-nm node for future high-speed transistor application is simulated. The Si-cap is assume to be relax and Ge layer is fully strained. For 90-nm node planar control-Si device, HALO implantation is necessary to reduce the SCEs. The Si-cap/Ge heterostructure results in the holes confinement in the quantum well, which provide better control ability comparing to control-Si device. The BTBT model for Ge is analyzed and put into simulation. The leakage due to smaller bandgap of Ge is examined by different Si-cap thickness and Ge layer thickness.