| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 96 === Content addressable memories (CAMs) are hardware-based parallel lookup tables with
bit-level masking capability. They are attractive for applications such as packet forwarding and
classification in network routers. Despite the attractive features of CAMs, high power consumption
is one of the most critical challenges faced by CAM designers, This work proposes circuit
techniques for reducing CAM power consumption. The main contribution of this work is reduction
in match line (ML) sensing energy, and static-power reduction techniques. The ML sensing energy
is reduced by employing positive-feedback ML sense amplifiers (MLSAs). We simulate the
circuit with TSMC 0.18 μm process at 1.8 V. The simulation results of the postive-feedback MLSA
show 86.3% reduction in ML power-delay product. Finally, design and analysis of a complete CAM
circuit are presented, and compared with other published designs.
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