NOR-type logic Content-Addressable Memory circuit of two segment matchline schem

碩士 === 國立臺灣大學 === 電機工程學研究所 === 96 === The design of the Low power VLSI circuit is one of the most important issues at the present time technology. In the chip, with ever increasing complexity of VLSI design and transistors, the power saving becomes the noteworthy challenge. In order to solve the pro...

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Main Authors: Tse-Chun Ou Yang, 歐陽策群
Other Authors: 賴飛羆
Format: Others
Language:en_US
Published: 2008
Online Access:http://ndltd.ncl.edu.tw/handle/49854084304074182006
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spelling ndltd-TW-096NTU054420592016-05-11T04:16:50Z http://ndltd.ncl.edu.tw/handle/49854084304074182006 NOR-type logic Content-Addressable Memory circuit of two segment matchline schem 兩級式匹配線反或邏輯型態之內容定址記憶體 Tse-Chun Ou Yang 歐陽策群 碩士 國立臺灣大學 電機工程學研究所 96 The design of the Low power VLSI circuit is one of the most important issues at the present time technology. In the chip, with ever increasing complexity of VLSI design and transistors, the power saving becomes the noteworthy challenge. In order to solve the problem of the power consumption, the Network-on-Chip is proposed to deal with the difficulties of inter-communication between IP cores. In the NoC, the main components are Switch (or so-called Router) and Network Interface (NI, or so-called Wrapper), and CAM (Content-Addressable Memory) is an indispensable part in the router. In this thesis, we propose a NOR-type logic Content-Addressable Memory circuit of two segment matchline scheme to Reduce power consumption, in this thesis, the proposed matching scheme can be saved about 70% on average power consumption. 賴飛羆 2008 學位論文 ; thesis 54 en_US
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language en_US
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description 碩士 === 國立臺灣大學 === 電機工程學研究所 === 96 === The design of the Low power VLSI circuit is one of the most important issues at the present time technology. In the chip, with ever increasing complexity of VLSI design and transistors, the power saving becomes the noteworthy challenge. In order to solve the problem of the power consumption, the Network-on-Chip is proposed to deal with the difficulties of inter-communication between IP cores. In the NoC, the main components are Switch (or so-called Router) and Network Interface (NI, or so-called Wrapper), and CAM (Content-Addressable Memory) is an indispensable part in the router. In this thesis, we propose a NOR-type logic Content-Addressable Memory circuit of two segment matchline scheme to Reduce power consumption, in this thesis, the proposed matching scheme can be saved about 70% on average power consumption.
author2 賴飛羆
author_facet 賴飛羆
Tse-Chun Ou Yang
歐陽策群
author Tse-Chun Ou Yang
歐陽策群
spellingShingle Tse-Chun Ou Yang
歐陽策群
NOR-type logic Content-Addressable Memory circuit of two segment matchline schem
author_sort Tse-Chun Ou Yang
title NOR-type logic Content-Addressable Memory circuit of two segment matchline schem
title_short NOR-type logic Content-Addressable Memory circuit of two segment matchline schem
title_full NOR-type logic Content-Addressable Memory circuit of two segment matchline schem
title_fullStr NOR-type logic Content-Addressable Memory circuit of two segment matchline schem
title_full_unstemmed NOR-type logic Content-Addressable Memory circuit of two segment matchline schem
title_sort nor-type logic content-addressable memory circuit of two segment matchline schem
publishDate 2008
url http://ndltd.ncl.edu.tw/handle/49854084304074182006
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