| Summary: | 碩士 === 臺灣大學 === 電機工程學研究所 === 96 === This thesis realizes a cyclic analog-to-digital converter with background digital calibration according to the split-ADC architecture proposed by McNeill in 2005. The purpose is to establish an experimental platform on which the A/D converter and digital calibration circuit can be integrated. The calibration algorithm adopted does not require extra calibration signal to be injected in to the converter’s signal path, and therefore minimizes its effect on the input signal. Also, with the help of digital calibration, the overhead of implementing the split-ADC architecture is reduced. It only increases two extra comparators compared with the traditional architecture.
The underlying calibration principle assumes the average of two adjacent A/D converters as the ideal conversion result. The converter then may be taken as an unknown system whose characteristics can be probed with an adaptive filter. Using the assumed ideal conversion results and the real conversion output, one may apply the least-mean-square method. In this way, the actual parameters of the individual ADCs is found, completing the digital calibration procedure.
The chip has been fabricated using 0.35 um CMOS process, occupying area of 1.5x1.5 mm2. Measurement results show that the split-ADCs exhibit resolution of 45.70 dB and 45.78 dB, equivalent to ENOB of 7.3 bits and 7.3 bits, respectively. The maximum DNL of the converters are 1.34 LSB and 1.15 LSB, and the maximum INL are 4.91 LSB and 4.89 LSB, respectively. (LSB unit is calculated assuming 10-bit resolution) Digital calibration circuit is realized on FPGA, with maximum achievable operating frequency of 30.44 MHz. After integration, the system improves the resolution from 45.94 dB to 54.43 dB, which equivalently improves ENOB from 7.33 to 8.74. Maximum DNL are 1.16 LSB and 1.15 LSB before and after calibration, respectively, and maximum INL drops from 4.38 LSB to 1.77 LSB.
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