| Summary: | 碩士 === 國立臺灣大學 === 電信工程學研究所 === 96 === In this dissertation, a mHEMT low noise amplifier (LNA) and three CMOS phase shifters are developed for radio astronomy receiver and phased-array system, respectively.
A 4-12 GHz LNA is an important building block at cold cartridge of ALMA (Atacama Large Millimeter/Sub-millimeter Array) radio astronomy receiver. Since the equivalent noise temperature of LNA affects the sensitivity of the received signal and dominates the performance of the receiver. In order to achieve the stringent noise requirement, the metamorphic HEMT technology employed to realize the LNA. It takes the advantages of low cost GaAs process and highly doped indium channel to achieve low noise performance. The on-chip measurements at room temperature with 160 mW dc consumption for LNA give a power gain of 29±1 dB and a minimum noise figure of 1.9 dB. After packaging, at room temperature the LNA with 20 mW dc consumption gives a power gain of 25±2 dB and a minimum noise figure of 1.9 dB. When cooled down to 22.4 K the LNA with 20 mW dc consumption shows a power gain of 25±2 dB and a minimum equivalent noise temperature of 15.1 K.
CMOS phased-array system is a future trend in modern communication system, since the CMOS technology reduce the fabrication cost by integrating both the RF front-end and baseband circuit in a single chip, and the special diversity and high array gain of phased-array system can increase the spectral efficiency of the system. However, to establish such system the performance of the phase shifter must be considered primarily. In this thesis, three different topologies of CMOS phase shifters will be introduced.
First of all, a miniature 3-bit switching phase shifter is presented. By shrinking the size of inductors, the size can be reduced to 0.285 mm2. The circuit is implemented with 0.18-μm CMOS technology. The circuit demonstrates RMS phase error less than 5.3° and RMS gain error less than 1.3 dB from 21-29 GHz. The average insertion loss and return loss at 24 GHz are 11 and 7 dB, respectively.
Further, a phase shifter based on the injection locked oscillator is designed and fabricated in a 0.18-μm CMOS technology, which has only 0.22 mm2 chip area and 14-mW power dissipation. Low quality factor design of the LC tank and wide tuning range design of free-running oscillator can extend the locking range up to 38% with -3 dBm input power and also reduces phase noise degradation of the locked oscillator in the phase tuning range. These features can enhance the feasibility and reliability of the injection locked oscillator based phase shifter in phased-array system.
Finally, a new architecture of vector sum phase shifter is designed and fabricated in a 0.13-μm CMOS technology. By lowering down supply voltage and reducing the number of amplifiers, the power dissipation can be reduced to 20 mW. Fewer passive components such as couplers and baluns can shrink the chip size to 0.45 mm2. The measured results demonstrate RMS phase errors of 1.5-10° and RMS gain errors of 1.2-1.6 dB from 17-24 GHz.
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