The Techniques and Implementations of the Broad-band Amplifiers for High-frequency Applications

• Main Authors: Chih-Kang Chien, 簡志剛
• Other Authors: Liang-Hung Lu
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/21970996823742183412

碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === Owing to the extensive requirement of data capacity, the communication system with high data rate has aroused much more attention. Broadband architecture is one of the important techniques for high speed application since it enables multi-channel transmissions simultaneously, and the wideband amplifier is usually the critical component among all of the building blocks. Besides, following the highly-developed Si-based process, various high speed systems are realized and integrated by CMOS technology. Now that the above descriptions are the significant trends in recent years, the researches and developments of high-frequency wideband amplifier in submicron CMOS process are quite a practical and challenged topic of the thesis. In order to realize the broadband techniques, a differential distributed amplifier (DA) is developed for OC-768 applications. The non-uniform design strategy is utilized and the inductive peaking cascode topologies are applied to improve the performance. According to the demonstrated references, the proposed differential DA is the only work able to operate in 40-Gb/s data rate in CMOS 0.18-μm process. Afterward, a transimpedance amplifier (TIA) with tunable 3-dB bandwidth is presented for optical communications. Within a broadband input loading and a wideband gain stage, a feedback loop is incorporated as the bandwidth-tuning mechanism. By tuning the bandwidth of the TIA, an optimum bit-error-rate (BER) can be achieved in the receiver frontend for high-speed data transmission. To complete a receiver front-end, a 10-Gb/s limiting amplifier (LA) is involved with modified Cherry-Hooper amplifier structure. By the inter-stage feedback mechanism, the bandwidth is further widened for the standard requirement. In comparison with the published works, the power consumption is enormously saved within the proposed LA architecture.