Transition Fault Diagnosis Using At-Speed Scan Patterns with Multiple Capture Clocks

Transition Fault Diagnosis Using At-Speed Scan Patterns with Multiple Capture Clocks

碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === This thesis presents a diagnosis technique to locate transition faults using scan patterns with multiple capture clocks which are applied at speed. To quickly locate the candidate faults, a two-level search is proposed. The circuit is first partitioned into fa...

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Bibliographic Details
Main Authors: Shang-Feng Chao, 趙上鋒
Other Authors: Chien-Mo Li
Format: Others
Language:zh-TW
Published: 2008
Online Access:http://ndltd.ncl.edu.tw/handle/72786852707305269971
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spelling ndltd-TW-096NTU054281152016-05-11T04:17:10Z http://ndltd.ncl.edu.tw/handle/72786852707305269971 Transition Fault Diagnosis Using At-Speed Scan Patterns with Multiple Capture Clocks 使用多重擷取時脈高速掃描測試圖樣的轉換錯誤診斷 Shang-Feng Chao 趙上鋒 碩士 國立臺灣大學 電子工程學研究所 96 This thesis presents a diagnosis technique to locate transition faults using scan patterns with multiple capture clocks which are applied at speed. To quickly locate the candidate faults, a two-level search is proposed. The circuit is first partitioned into fanout-free regions (FFR’s), which are then partitioned into FFR groups. This technique uses the unknown “X” to model the fault effect so the fault size does not affect the diagnosis results. Experiments on ISCAS’89 large benchmark circuits with Intel 64-bit 2.0 GHz CPU show that, on the average, all transition faults are accurately diagnosed in 21 seconds using test patterns of six capture clocks. The proposed technique is suitable for small delay defects that cannot be diagnosed using slow speed scan test patterns with a single capture clock. Chien-Mo Li 李建模 2008 學位論文 ; thesis 57 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === This thesis presents a diagnosis technique to locate transition faults using scan patterns with multiple capture clocks which are applied at speed. To quickly locate the candidate faults, a two-level search is proposed. The circuit is first partitioned into fanout-free regions (FFR’s), which are then partitioned into FFR groups. This technique uses the unknown “X” to model the fault effect so the fault size does not affect the diagnosis results. Experiments on ISCAS’89 large benchmark circuits with Intel 64-bit 2.0 GHz CPU show that, on the average, all transition faults are accurately diagnosed in 21 seconds using test patterns of six capture clocks. The proposed technique is suitable for small delay defects that cannot be diagnosed using slow speed scan test patterns with a single capture clock.
author2 Chien-Mo Li
author_facet Chien-Mo Li
Shang-Feng Chao
趙上鋒
author Shang-Feng Chao
趙上鋒
spellingShingle Shang-Feng Chao
趙上鋒
Transition Fault Diagnosis Using At-Speed Scan Patterns with Multiple Capture Clocks
author_sort Shang-Feng Chao
title Transition Fault Diagnosis Using At-Speed Scan Patterns with Multiple Capture Clocks
title_short Transition Fault Diagnosis Using At-Speed Scan Patterns with Multiple Capture Clocks
title_full Transition Fault Diagnosis Using At-Speed Scan Patterns with Multiple Capture Clocks
title_fullStr Transition Fault Diagnosis Using At-Speed Scan Patterns with Multiple Capture Clocks
title_full_unstemmed Transition Fault Diagnosis Using At-Speed Scan Patterns with Multiple Capture Clocks
title_sort transition fault diagnosis using at-speed scan patterns with multiple capture clocks
publishDate 2008
url http://ndltd.ncl.edu.tw/handle/72786852707305269971
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AT zhàoshàngfēng transitionfaultdiagnosisusingatspeedscanpatternswithmultiplecaptureclocks
AT shangfengchao shǐyòngduōzhòngxiéqǔshímàigāosùsǎomiáocèshìtúyàngdezhuǎnhuàncuòwùzhěnduàn
AT zhàoshàngfēng shǐyòngduōzhòngxiéqǔshímàigāosùsǎomiáocèshìtúyàngdezhuǎnhuàncuòwùzhěnduàn
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