Transition Fault Diagnosis Using At-Speed Scan Patterns with Multiple Capture Clocks
碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === This thesis presents a diagnosis technique to locate transition faults using scan patterns with multiple capture clocks which are applied at speed. To quickly locate the candidate faults, a two-level search is proposed. The circuit is first partitioned into fa...
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| Format: | Others |
| Language: | zh-TW |
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2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/72786852707305269971 |
| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === This thesis presents a diagnosis technique to locate transition faults using scan patterns with multiple capture clocks which are applied at speed. To quickly locate the candidate faults, a two-level search is proposed. The circuit is first partitioned into fanout-free regions (FFR’s), which are then partitioned into FFR groups. This technique uses the unknown “X” to model the fault effect so the fault size does not affect the diagnosis results. Experiments on ISCAS’89 large benchmark circuits with Intel 64-bit 2.0 GHz CPU show that, on the average, all transition faults are accurately diagnosed in 21 seconds using test patterns of six capture clocks. The proposed technique is suitable for small delay defects that cannot be diagnosed using slow speed scan test patterns with a single capture clock.
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