Cost Efficient MIMO Equalization Design for MIMO WLAN and FFT/IFFT Hardware Implementation

• Main Authors: Yi-Hsien Lin, 林宜賢
• Other Authors: 汪重光
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/00305414573379038302

碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === The high data-rate wireless transmission is the demand for many multimedia applications. For this purpose, IEEE 802.11n is the wireless LAN standard to offer higher throughput based on MIMO-OFDM techniques. In this thesis, a digital baseband receiver is presented for IEEE 802.11n, including the initial boundary detection, synchronization tracking loop, FFT, and MIMO equalization. For MIMO transmission schemes, Alamouti and VBLAST are presented here. Furthermore, the combined scheme is taken to achieve both of the advantages, i.e. higher data rate and better quality. The combined scheme can satisfy a 100Mbps requirement of IEEE 802.11n standard. Based on strength-reduced complex multiplication, a cost e cient MISO/MIMO equalization is proposed for Alamouti scheme. The cost efficient MISO/MIMO equalization contains three parts: channel estimation, MISO/MIMO detection and updating process. The overall algorithm can reduce 32 % multiplication complexity in general case compared with 33 % in 11n case. The system performance of this design is the same as the conventional technique evaluated by the uncoded SER simulation over indoor multipath fading channel. Finally, a 64-point SISO FFT/IFFT processor is realized in the chip design and evaluated by FPGA board. By analyzing the system performance, the parameters of FFT/IFFT can be derived for SDF pipeline structure. By multiplierless design and memory arrangement, the chip core area occupies 0.570 mm x 0.565 mm and consumes 10.8 mW at operating frequency 40MHz using 0.18 um CMOS technology. The FFT/IFFT functionality is also veri ed by Altera Stradix EP1S80 FPGA board and Tektronix TLA 715.