| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === There are two parts in this thesis. The first part is about the fundamental shape extraction from layout of microwave multi-layer circuit and the generation of net-list diagram. This part applies methodologies of computational geometry to design algorithms to identify the fundamental shapes from layout of circuit, and then connect all fundamental shapes into a complete net-list diagram. The second part is the post-applications of the net-list diagram. The main applications in this thesis are direct current path connectivity check, capacitor structure identification, capacitance estimation, inductor structure identification, inductor segment information extraction, and automatic layout-based schematic generation. The fundamental shapes include rectangles and simple polygons and the extractable circuit components include capacitors, wires, inductors, vias, ports, and ground. These two parts formed the front-end of Layout Versus Schematic (LVS) checking.
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