| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === In the thesis, a 2x2 MIMO OFDM digital baseband receiver for IEEE 802.16-2004 WMAN-OFDM PHY applications is designed. The hardware implementation of a 256-point 2x2 MIMO FFT/IFFT processor is also presented.
The inner receiver design includes the symbol boundary detection, CP mode detection, CFO/SFO estimation/compensation, phase compensation, MIMO channel estimation, Alamouti-scheme STBC detector and BLMS adaptive equalization. Based on the format of space-time coding (STC) preamble, the frequency response of the 2x2 MIMO channel can be easily estimated by performing least-square (LS) estimation and piecewise-parabolic interpolation. On the other hand, the BLMS algorithm is derived to adaptively track the estimated channel coefficients for the Alamouti-scheme STBC frequency-domain equalizer (FEQ). According to the simulation results, the 2x2 STBC-based BLMS adaptive FEQ can achieve superior improvement of the SER performance over non-adaptive ones. Subsequently, a cost efficient MIMO FFT/IFFT processor for IEEE 802.16 WMAN is presented. Considering the conventional radix-2 pipeline architectures, the hardware utilization is only 50%. However, by applying the proposed dataflow scheduling (DS) technique, the effective hardware utilization can be raised to 100%. Therefore, a single butterfly unit within each pipeline stage is sufficient to deal with the two data sequences, and the hardware complexity is significantly reduced. Besides, the single-port register files are employed for the large-size delay buffers in order to lower the area cost and power consumption. The hardware-sharing technique is also applied to reduce the required complex multipliers.
In addition, the design of a modified complex multiplier is presented. Some hardware design techniques are applied, including the data mapping scheme, signed-digit representation and common-term sharing between the real and the imaginary parts of the twiddle factor. The modified complex multiplier requires only 65% of the cell area compared with the conventional one.
The proposed FFT/IFFT processor has been emulated on the FPGA board. The SQNR performance is over 44 dB for QPSK and 16/64-QAM signals, which can achieve 0.1 dB of implementation loss. Furthermore, a test chip has been designed using standard 0.18-um CMOS technology with a core area of 887x842 um^2. According to the post-layout simulation results, the design consumes 46 mW under 1.8 V supply voltage at 64 MHz operating frequency.
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