Statistical Circuit Optimization using Simultaneous Gate and Wire Sizing
碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === Due to the technology scaling down, process variation has become a crucial challenge on both interconnect delay and reliability. To handle the process variation, statistical optimization has emerged as a popular technique for yield improvement. Both second-order...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/60775478013903001331 |