| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === Due to the technology scaling down, process variation has become a crucial challenge on both interconnect delay and reliability. To handle the process variation, statistical optimization has emerged as a popular technique for yield improvement. Both second-order conic programming (SOCP) and Lagrangian relaxation (LR) have been proposed in the literature for statistical circuit optimization by gate sizing. However, not much work is on interconnect variation. In this thesis, we present the first work to use statistical methods to optimize the circuit area under timing, thermal, and power constraints by simultaneous gate and interconnect sizing. We apply both SOCP and LR to handle statistical circuit optimization and conduct comparative studies on these two methods. Our studies show significant limitations of SOCP in its flexibility, accuracy, and scalability for statistical circuit optimization, especially for interconnects. Compared with SOCP, experimental results show that the LR-based algorithm can achieve much better solution quality by reducing 33% area and obtain a 560X speedup over SOCP. The results demonstrate that LR is a better technique for multi-constrained statistical circuit optimization by both gate and wire sizing.
|
|---|
