Verification Environment for I/O Virtualization
碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === With the rapidly progressing Integrated Circuit (IC) technology, the functional verification becomes the bottleneck of development for Application-Specific Integrated Circuits (ASIC). Since a complete verification methodology, such as formal verification, is ver...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/61641665183046971502 |