| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === Technology mapping aims at searching an optimal implementation for a Boolean netlist using gates from a technology library. Compared with its $NP$-complete area minimization counterpart, DAG mapping for delay minimization is considered much sophisticated because matching choices must be made without knowing actual arrival times and output loads. Traditional approaches to this problem involve too many approximate simplifications, and are far from accurate. They either use tree mapping, but not DAG mapping, or apply a load-independent timing model, but not a load-dependent timing model to obtain a mapped netlist.
Unlike traditional approaches, this thesis tackles this problem directly under load-dependent DAG mapping. The enabling techniques for accurate optimization include on-the-fly load-estimation refinement, breadth-first backward covering for load consolidation, and use of a piecewise linear model for accurate timing calculation.
This new technology mapping algorithm is evaluated through several experiments. They include comparisons for delay and area, for run times, for load-estimation heuristics, etc. Experimental results show that our method outperforms the state-of-the-art mapper by 38.9\% in delay, with 10.8\% increase in area, on average for large benchmark circuits. Meanwhile, our method can be finished within few seconds, even for large circuits. Thus, our new algorithm can not only effectively reduce circuit delay with an accurate estimation, but also efficiently obtain a mapping solution.
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