Design of Continuous-Time Delta-Sigma Modulators for Wireless Applications

• Main Authors: Chan-Hsiang Weng, 翁展翔
• Other Authors: Tsung-Hsien Lin
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/72068133171218991762

碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === In the first work, a dual-mode second-order continuous-time delta-sigma ADC is designed and implemented. In order to achieve low-voltage, and low-power design, the sliding quantizer is implemented to save the number of the comparator. The resonator is also included to adjust the center frequency of the signal to achieve low-pass and band-pass operation. This modulator is implemented in the TSMC 0.13-μm COMS process. The simulated peak SNR of the proposed modulator achieves more than 60-dB with 1-MHz bandwidth at a 60-MHz sampling rate. The center frequency is about 0 MHz (low-pass mode) and 2 MHz (band-pass mode). The implemented modulator consumes 2 mW from a 1.2-V supply. Designed for a wide-band application, a second-order multi-bit continuous-time delta-sigma modulator is presented in the second part of this thesis. In the modulator, in order to compensate for the excess loop delay, a passive compensation technique is proposed. The additional compensation path in the modulator can compensate for the movement of poles and zeros that caused by excess loop delay. The fast compensation circuits stabilize the system when the modulator operates in high speed state. This delta-sigma modulator is implemented in the TSMC 0.13-μm COMS process. The proposed modulator achieves a 36-dB peak SNR with a 15-MHz bandwidth at a 500-MHz sampling rate and has a 38-dB dynamic range. The implemented modulator consumes 36 mW from a 1.2-V supply. The proposed continuous-time delta-sigma modulator is suitable for wireless wideband systems.