Design and Implementation of Dual-Diagonal Structured LDPC Encoder Based on Parity Bit Prediction and Correction
碩士 === 國立臺灣大學 === 資訊工程學研究所 === 96 === In this thesis, an e cient encoding scheme for dual-diagonal structured LDPC codes is proposed. Our encoding algorithm employs parity bit prediction and correction to break up the data dependency within the encoding process. The parallel encoder can achieve high...
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| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/09705684413248426415 |
| Summary: | 碩士 === 國立臺灣大學 === 資訊工程學研究所 === 96 === In this thesis, an e cient encoding scheme for dual-diagonal structured LDPC codes is proposed. Our encoding algorithm employs parity bit prediction and correction to break up the data dependency within the encoding process. The parallel encoder can achieve higher level of parallelism and better hardware utilization, and the serial encoder can achieve low hardware cost. The number of required clock cycles for encoding one codeword can be reduced to achieve higher throughput performance. The proposed scheme can be directly applied to IEEE 802.11n and 802.16e dual-diagonal codes without any matrix modi cation. A low-complexity encoder architecture is proposed and implemented to verify these characteristics. Results show that the proposed architecture outperforms conventional works in terms of throughput and throughput/area ratio.
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