Detour Output Buffer of High-Performance RoCo Decoupled Router for Network-on-Chip
碩士 === 國立臺灣大學 === 資訊工程學研究所 === 96 === The scaling of microchip technologies has enabled large scale systems-on-chip(SoC). With ever increasing complexity of design and IP cores, the inter-communication between IP cores becomes the noteworthy challenge. In order to solve the problem of the data commu...
Main Authors: | Po-Shan Huang, 黃柏舜 |
---|---|
Other Authors: | 李秀惠 |
Format: | Others |
Language: | en_US |
Published: |
2008
|
Online Access: | http://ndltd.ncl.edu.tw/handle/96705213767866780491 |
Similar Items
-
SB-Router: A Swapped Buffer Activated Low Latency Network-on-Chip Router
by: Monika Katta, et al.
Published: (2021-01-01) -
Buffer-Stealing Router Design for Improved Communication Efficiency in Network-on-Chip
by: Wan-Ting Su, et al.
Published: (2010) -
A Performance Analytical Strategy for Network-on-Chip Router with Input Buffer Architecture
by: WANG, J., et al.
Published: (2012-11-01) -
Design of a Partially Buffered Crossbar Router for Mesh-based Network-on-Chips
by: Zhi-Chun Jao, et al.
Published: (2011) -
Design of an asynchronous router for Network on Chip
by: Ding Luen Huang, et al.
Published: (2008)