| Summary: | 碩士 === 國立臺灣大學 === 資訊工程學研究所 === 96 === The scaling of microchip technologies has enabled large scale systems-on-chip(SoC). With ever increasing complexity of design and IP cores, the inter-communication between IP cores becomes the noteworthy challenge. In order to solve the problem of the data communication, the Network-on-Chip is proposed to deal with the difficulties of inter-communication between IP cores.Network-on-chip (NoC) research addresses global communication in SoC. The low latency design is one of the most important issues to on-chip network design and the implementation of scalable communication structures. In the NoC, the main component is router. In this thesis, we propose a low-latency decomposed router used in the 2D mesh topology and, we can accomplish the goal of the high performance using detour output buffer (DOB). According to the experimental results, with the method mentioned in this thesis, the latency reduction can be achieved about 6% with light overhead on hardware and energy consumption. In this work, we can effectively increase the utilization of router to reduce the network congestion of the global communication.
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