| Summary: | 碩士 === 國立臺灣大學 === 資訊工程學研究所 === 96 === System-on-chip design has been commonly used in modern circuit design in multimedia, telecommunications and consumer electronics domain. With the technology scales down, more IP cores can be integrated into a single ship. The interconnection between IP becomes the performance bottleneck. Network-on-chip (NoC) which is packet switch based communication is proposed to overcome the SoC interconnection problem. The NoC router (or so-called switch) is the fundamental component in NoC architecture, all the functionality and property of NoC is dominated by the router design. The most influence to network performance in router design is the buffer resource. However, under real application the buffer usage will be unbalanced and utilized inefficiently. In this thesis, we introduce a novel dynamic buffer allocating method with our router architecture organized by separate buffers to achieve shared buffer purpose. Moreover, we conquer the shortcoming of single buffer router and utilize the buffer resource efficiently. Experimental results show that we can achieve the same performance of conventional architecture in NoC while using only 60% buffer size.
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