The Thermal Simulation and Process of the Flexible TFTs and Integrated Circuit for Next-Generation

碩士 === 國立臺灣師範大學 === 光電科技研究所 === 96 === In this century, thin film transistors (TFTs) and integrated circuits (ICs) have been developed extensively and used in many electronics applications and designs with a range of different structures. Among these research, thermal management would be considered...

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Main Authors: Yung-Tsung Liu, 劉永宗
Other Authors: Min-Hung Lee
Format: Others
Language:en_US
Published: 2008
Online Access:http://ndltd.ncl.edu.tw/handle/rc6wxz
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spelling ndltd-TW-096NTNU56140052019-05-15T19:38:21Z http://ndltd.ncl.edu.tw/handle/rc6wxz The Thermal Simulation and Process of the Flexible TFTs and Integrated Circuit for Next-Generation 下世代軟性薄膜電晶體與積體電路之熱傳模擬及其製程研究 Yung-Tsung Liu 劉永宗 碩士 國立臺灣師範大學 光電科技研究所 96 In this century, thin film transistors (TFTs) and integrated circuits (ICs) have been developed extensively and used in many electronics applications and designs with a range of different structures. Among these research, thermal management would be considered and played a critical role when devices during operation or in fabrication process. Thermal accumulation effects may lead to failure in manufacturing process and devices performance degradation. Therefore, we propose thermal improvement for these conditions and utilize ISE TCAD simulation to obtain the temperature distribution and profile. In chapter 1, we first introduce the course of change and development for flexible a-Si:H thin-film transistor and recent three-dimensional integrated circuits (3D-ICs) fabrication. Furthermore, motivation and organization of thesis will be explored. In chapter 2, we utilize TCAD simulation to verify that flexible a-Si:H TFT with thermal conduction layer such as copper (Cu), aluminum (Al), molybdenum (Mo) can efficient to dissipate more heat and lower device temperature during bias stress operation. In chapter 3, we first propose one structure, which has a thermal conduction layer such as Cu in ILD oxide layer for monolithic 3D-ICs. Then TCAD simulation was performed by solving the temperature distribution for 2D model during laser-induced epitaxial growth (LEG) process. In chapter 4, we make a description of fabrication process for Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) by lithography technique with only one mask definition. The operating instructions, principle of related instruments and design of mask pattern for Via arrays also be later summarized. In chapter 5, at the end of this thesis, we will make conclusions and future works. Min-Hung Lee 李 敏 鴻 2008 學位論文 ; thesis 76 en_US
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description 碩士 === 國立臺灣師範大學 === 光電科技研究所 === 96 === In this century, thin film transistors (TFTs) and integrated circuits (ICs) have been developed extensively and used in many electronics applications and designs with a range of different structures. Among these research, thermal management would be considered and played a critical role when devices during operation or in fabrication process. Thermal accumulation effects may lead to failure in manufacturing process and devices performance degradation. Therefore, we propose thermal improvement for these conditions and utilize ISE TCAD simulation to obtain the temperature distribution and profile. In chapter 1, we first introduce the course of change and development for flexible a-Si:H thin-film transistor and recent three-dimensional integrated circuits (3D-ICs) fabrication. Furthermore, motivation and organization of thesis will be explored. In chapter 2, we utilize TCAD simulation to verify that flexible a-Si:H TFT with thermal conduction layer such as copper (Cu), aluminum (Al), molybdenum (Mo) can efficient to dissipate more heat and lower device temperature during bias stress operation. In chapter 3, we first propose one structure, which has a thermal conduction layer such as Cu in ILD oxide layer for monolithic 3D-ICs. Then TCAD simulation was performed by solving the temperature distribution for 2D model during laser-induced epitaxial growth (LEG) process. In chapter 4, we make a description of fabrication process for Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) by lithography technique with only one mask definition. The operating instructions, principle of related instruments and design of mask pattern for Via arrays also be later summarized. In chapter 5, at the end of this thesis, we will make conclusions and future works.
author2 Min-Hung Lee
author_facet Min-Hung Lee
Yung-Tsung Liu
劉永宗
author Yung-Tsung Liu
劉永宗
spellingShingle Yung-Tsung Liu
劉永宗
The Thermal Simulation and Process of the Flexible TFTs and Integrated Circuit for Next-Generation
author_sort Yung-Tsung Liu
title The Thermal Simulation and Process of the Flexible TFTs and Integrated Circuit for Next-Generation
title_short The Thermal Simulation and Process of the Flexible TFTs and Integrated Circuit for Next-Generation
title_full The Thermal Simulation and Process of the Flexible TFTs and Integrated Circuit for Next-Generation
title_fullStr The Thermal Simulation and Process of the Flexible TFTs and Integrated Circuit for Next-Generation
title_full_unstemmed The Thermal Simulation and Process of the Flexible TFTs and Integrated Circuit for Next-Generation
title_sort thermal simulation and process of the flexible tfts and integrated circuit for next-generation
publishDate 2008
url http://ndltd.ncl.edu.tw/handle/rc6wxz
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