FPGA Implementation of Competitive Learning with Partial Distance Search

FPGA Implementation of Competitive Learning with Partial Distance Search

碩士 === 國立臺灣師範大學 === 資訊工程研究所 === 96 === This paper presents a novel algorithm for the field programmable gate array (FPGA) realization of the competitive learning (CL) algorithm with k-winners-take-all activation. The k winning neurons for updating are those best matching the input vector in the wave...

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Bibliographic Details
Main Authors:	Hui-Ya Li, 李惠雅
Other Authors:	Wen-Jyi Hwang
Format:	Others
Language:	zh-TW
Published:	2008
Online Access:	http://ndltd.ncl.edu.tw/handle/27233278801190987356

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