| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 96 === With the advance of process technology, the purposes of the low power and high performance are focused in the nowadays circuit design. In digital circuit designs, the cell-based design follow is the most common way to implement the chip, and standard libraries play an important role in the cell-based flow. The standard logic cell library among different cell libraries is the major library to construct large of circuits. For digital circuit designers, using the low power cell library is the simplest and fast method to achieve the low power purpose. There are some low power techniques in the cell library, and the most efficient method is to reduce the supply voltage in the cell library.
In order to develop low voltage cell library, the standard cells need special design considerations in the low voltage condition. This thesis focuses on sequential cells of standard cells in low voltage condition. The main function of sequential cells is the data saving and clearing with the control of clock and reset signals, and then sequential cells have larger dynamic power consumption then the other cells. Consequently, it is necessary to research in sequential cells with low voltage condition. Additionally, the cell library characterization flow also needs the special setting for low voltage applications.
With low voltage affections, the cell library constraints become more serious.
For low power and high performance issues, the best application with low voltage cell library is the circuits with multiple power domains. Using the normal cell library in the critical circuits is for high performance consideration, and the non-critical circuits are implemented by the low voltage cell library in order to reduce unnecessary power consumption. In this thesis, it describes achievements of single-power and multi-power circuit designs. According to the results of the test chip, the total power consumption is decreased 68% by supply voltage dropping.
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