| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 96 === This thesis proposes the design of a fast-switching frequency synthesizer, which includes an on-chip adaptive-bandwidth loop filter, a VCO with digital varactor array, programmable frequency divider, phase-frequency detector, tunable charge pump, jitter measurement circuit and loop bandwidth decision circuit. The main target is to achieve fast-locking frequency change and highly integration. The on-chip loop filter adopts a cascode current mirror architecture, which effectively shrinks the needs of capacitance, and in advance reduces the occupied area. For the stability of the phase-locked loop, the charge pump current is adjusted according to the loop bandwidth setting. The jitter measurement and loop decision circuit are used for switching the loop bandwidth, and thus achieve a fast-locking behavior. The frequency divider is realized by a multi-modulus prescaler with division number 64 to 127. The fully integrated frequency synthesizer is implemented in TSMC 0.18 μm CMOS process. The measured frequency tuning range is from 1.6956 GHz to 1.710 GHz. The locking time is around 84 μs. The total chip area is 1.188 x 0.998 and the power consumption is 24.4mA.
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