Design of Ultra Low Power Current-Mode Logics with Adaptive Body Bias

• Main Authors: Hsiang-Ju Hsu, 許翔如
• Other Authors: Yarsun Hsu
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/86237054206390502898

碩士 === 國立清華大學 === 電機工程學系 === 96 === With the demand of high transmission rate, there is a tendency toward current-mode logic (CML) circuits in communication systems. Although CML circuits are of high speed performance, the sustained current source consumes static power substantially. However, because the power-delay product (PDP) of the conventional CML circuits is approximate to a constant with varying supply voltage, i.e. the power-delay tradeoff, the conventional CML circuits is difficult to reducing power dissipations while maintaining high speed through the traditional low power techniques. In the recent years, there have been some low power methodologies published for CML circuits. However, they save power consumption either by scarifying swing voltage of differential output signals or by losing high speed performance. It means that the intrinsic problem of the conventional CML circuits has not been broken through yet. In this thesis, a novel adaptive body biasing (ABB) circuit is proposed for ultra low power CML circuits. In the design, body bias self-adjusts depending on the differential input signals and applies to the source-coupled pairs in CML circuits. By switching body bias alternately, the margin for lowering power through reducing supply voltage VDD is originated from the increased voltage swing of the differential output signals. Through the proposed clocked-power ABB circuit, the supply voltage VDD and the dc-level of the differential inputs can be reduced significantly while maintaining the original voltage swing of differential output signals and the original transmission rate. The architecture can reach power saving up to 60%, and 50% on average with the breaking of power-delay tradeoff. The design methodology and performance analysis for the low power ABB CML Buffers, MUXs, and Latches are presented in the thesis. The same design concept can also be extended to circuits composed of differential input pairs.