多處理器系統單晶片量測架構設計與實作

碩士 === 國立清華大學 === 資訊系統與應用研究所 === 96 === With the growing complexity and the improvement in embedded systems, MPSoC (Multiprocessor System-on-Chip) has become a new trend of embedded architecture design. As a result, the mechanisms of performance monitoring to effectively monitor these systems and fi...

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Bibliographic Details
Main Authors: Po-Hui Chen, 陳伯煇
Other Authors: Chung-Ta King
Format: Others
Language:en_US
Online Access:http://ndltd.ncl.edu.tw/handle/54977053542351449583
Description
Summary:碩士 === 國立清華大學 === 資訊系統與應用研究所 === 96 === With the growing complexity and the improvement in embedded systems, MPSoC (Multiprocessor System-on-Chip) has become a new trend of embedded architecture design. As a result, the mechanisms of performance monitoring to effectively monitor these systems and find out the performance bottlenecks are in great need. Currently, most of the open source MPSoC prototyping systems do not have special hardware supports for programmers to analyze, or to tune their target applications. Besides, with the increasing number of processors within a single chip, it would be more difficult and complex to do performance measurement. In this thesis, we propose a multiprocessor profiling architecture, ‘MPPA’, which helps programmers to analyze the low-level events within their multiprocessor systems. With the profiling architecture, it is possible to monitor all processors and system-wide events concurrently in a prototyping multiprocessor system. In addition, our design is less intrusive to the target system design since new instructions or extra dedicated bus are not necessary. Therefore our lightweight architecture keeps the design as simple and as small as possible. We implement this architecture into the Gaisler Leon3 open source embedded platform and realize the multiprocessor system on a Xilinx ML501 FPGA board. Evaluation results show that the proposed architecture is able to extract the low-level events, which help programmers to characterize target applications more easily and have sufficient information to find the performance bottlenecks while, and it meets the requirements of simple, flexible, and less intrusive design.