迷宮繞線與在迴轉率及障礙物限制下作最小成本之緩衝器嵌入
碩士 === 國立清華大學 === 資訊工程學系 === 96 === With the advanced VLSI technology, sharp slew rate and low power comsumption are often required in integrated circuit design. Timing buffering on non-critical nets may result in extra power dissipation and waste of buffering resource. Unfortunately, most previous...
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| Format: | Others |
| Language: | en_US |
| Online Access: | http://ndltd.ncl.edu.tw/handle/70513903768974191690 |