Fabrication and characterization of micro inductors on silicon substrate

博士 === 國立清華大學 === 材料科學工程學系 === 96 === In order to reduce the size of high-frequency communication devices, the general technology trend is to integrate both the active and passive components in the same substrate. The active components are generally fabricated on low resistivity silicon substrate. H...

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Main Authors: Chih-Ming Tai, 戴志銘
Other Authors: Chien-Neng Liao
Format: Others
Language:en_US
Published: 2008
Online Access:http://ndltd.ncl.edu.tw/handle/61116982338575185025
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spelling ndltd-TW-096NTHU51590122015-10-13T14:08:18Z http://ndltd.ncl.edu.tw/handle/61116982338575185025 Fabrication and characterization of micro inductors on silicon substrate 矽基材微型電感製備與特性分析 Chih-Ming Tai 戴志銘 博士 國立清華大學 材料科學工程學系 96 In order to reduce the size of high-frequency communication devices, the general technology trend is to integrate both the active and passive components in the same substrate. The active components are generally fabricated on low resistivity silicon substrate. However, silicon-based on-chip inductors usually suffer serious quality factor degradation at high frequency due to capacitive coupling in silicon substrates. Therefore, the goal of the study is to focus on how to improve the quality factor and inductance density of Si-based inductors. In order to reduce inductor’s substrate loss, we use thick low-k dielectric or air-bridge technology to isolate the silicon substrate as well as thick electroplating copper to reduce the series resistance of the inductor. Since the inductance and quality factor also depend on the dimensions of inductors, we have designed inductors with various dimensions to study the relationship between inductors’ properties and their physical dimensions. For conventional planar spiral inductors, the way to raise the inductance-to-area ratio is to increase the number of metal turns. However, the cost to be paid is the increased parasitic capacitance and the reduced quality factor of the spiral inductors. A double-level inductor fabricated by standard integrated circuits technology has been proposed to increase the inductance density. Nevertheless, it has low quality factor mainly due to the severe parasitic capacitance between conductor levels. Therefore, we fabricate double-level suspended inductors with large inter-level spacing, which can effectively reduce the parasitic capacitance and result in high quality factor. The other way to enhance inductance density is to integrate magnetic materials with inductors. Although inductors with magnetic materials have better inductance, they have a decreased quality factor due to the increasing series resistance. In addition to the inductor’s property enhancement, an appropriate device circuit model for predicting inductor’s properties is also important. One approach employed here is to utilize a data fitting technique to obtain the series inductance and resistance values of a spiral inductor. The other equivalent circuit components are calculated from the materials properties and physical dimensions of the inductor. Therefore, the designers would be able to determine quickly the inductor properties of the spiral inductors of interests from the results of the limited tested structures. The other inductor’s physical model is devised for simulating the properties of solenoid inductors. All the inductive, resistive, and capacitive equivalent circuit elements can be correlated to the physical parameters and material properties of the solenoid inductors. Chien-Neng Liao 廖建能 2008 學位論文 ; thesis 105 en_US
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description 博士 === 國立清華大學 === 材料科學工程學系 === 96 === In order to reduce the size of high-frequency communication devices, the general technology trend is to integrate both the active and passive components in the same substrate. The active components are generally fabricated on low resistivity silicon substrate. However, silicon-based on-chip inductors usually suffer serious quality factor degradation at high frequency due to capacitive coupling in silicon substrates. Therefore, the goal of the study is to focus on how to improve the quality factor and inductance density of Si-based inductors. In order to reduce inductor’s substrate loss, we use thick low-k dielectric or air-bridge technology to isolate the silicon substrate as well as thick electroplating copper to reduce the series resistance of the inductor. Since the inductance and quality factor also depend on the dimensions of inductors, we have designed inductors with various dimensions to study the relationship between inductors’ properties and their physical dimensions. For conventional planar spiral inductors, the way to raise the inductance-to-area ratio is to increase the number of metal turns. However, the cost to be paid is the increased parasitic capacitance and the reduced quality factor of the spiral inductors. A double-level inductor fabricated by standard integrated circuits technology has been proposed to increase the inductance density. Nevertheless, it has low quality factor mainly due to the severe parasitic capacitance between conductor levels. Therefore, we fabricate double-level suspended inductors with large inter-level spacing, which can effectively reduce the parasitic capacitance and result in high quality factor. The other way to enhance inductance density is to integrate magnetic materials with inductors. Although inductors with magnetic materials have better inductance, they have a decreased quality factor due to the increasing series resistance. In addition to the inductor’s property enhancement, an appropriate device circuit model for predicting inductor’s properties is also important. One approach employed here is to utilize a data fitting technique to obtain the series inductance and resistance values of a spiral inductor. The other equivalent circuit components are calculated from the materials properties and physical dimensions of the inductor. Therefore, the designers would be able to determine quickly the inductor properties of the spiral inductors of interests from the results of the limited tested structures. The other inductor’s physical model is devised for simulating the properties of solenoid inductors. All the inductive, resistive, and capacitive equivalent circuit elements can be correlated to the physical parameters and material properties of the solenoid inductors.
author2 Chien-Neng Liao
author_facet Chien-Neng Liao
Chih-Ming Tai
戴志銘
author Chih-Ming Tai
戴志銘
spellingShingle Chih-Ming Tai
戴志銘
Fabrication and characterization of micro inductors on silicon substrate
author_sort Chih-Ming Tai
title Fabrication and characterization of micro inductors on silicon substrate
title_short Fabrication and characterization of micro inductors on silicon substrate
title_full Fabrication and characterization of micro inductors on silicon substrate
title_fullStr Fabrication and characterization of micro inductors on silicon substrate
title_full_unstemmed Fabrication and characterization of micro inductors on silicon substrate
title_sort fabrication and characterization of micro inductors on silicon substrate
publishDate 2008
url http://ndltd.ncl.edu.tw/handle/61116982338575185025
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