Building the Golden Die Analytical Model at R&D Stage with WAT Parameters in Semiconductor Manufacturing

• Main Authors: Chi-Sheng Chang, 張其聖
• Other Authors: 陳飛龍
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/86787840675723173599

碩士 === 國立清華大學 === 工業工程與工程管理學系 === 96 === For semiconductor manufacturing industries, they usually have formed very high production costs because of the complicated manufacturing process of the manufacturing environment and expensive equipments. Almost every semiconductor company expects to reduce costs and enhance yield by applying the relative analytical techniques for its complex manufacturing steps. However, at the R&D stage of semiconductor fabrication, they always test the whole dies of one wafer in order to reach the highest accuracy. That is extremely time-consuming and labor intensive because of thousands of hundreds WAT parameters produced at the stage. Thus, it would be very beneficial to reduce costs if we can develop an analytical model suitable for this stage based on the relative WAT collecting data. This paper proposed an analytical model to find the “Golden Dies” of the relative wafer with WAT data at the R&D stage of semiconductor fabrication. The analytical model consists of three steps. First, the correlation matrix and the QC chart are utilized to reduce dimensions of raw WAT data collected from EDA to determine the representative dies of the wafer. The second step uses a known neural network architecture known as SOM to generate clusters within it. At final step, City-Block Distance Measure is applied to find out the golden dies of each cluster. Experimental results show that the proposed methodology can classify all dies into nine groups and successfully find out the golden dies.