The Design Verification Methodology for an Advanced Microprocessor

• Main Authors: Jing-Kun Zhong, 鐘靜昆
• Other Authors: Ing-Jer Huang
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/39503254248467764023

碩士 === 國立中山大學 === 資訊工程學系研究所 === 96 === According to references, testing and verification of a hardware circuit project occupy about 60%˜70% of project time. Now that product cycle time is decreasing, verification methodology is an important parameter for effective and successful completion of a design project. Enhanced processor functions also make verification conditions more difficult. In this thesis the processor SYS32IME III, which is constructed based on architecture of ARM 1022E, is verified by using V5TE instruction set. This thesis focus on processor verification flow and others to help verification method. The verification language that is used to help generate testbench are described in this paper. Also, corner cases are generated, producing test cases that may be reused in different verification environments. Lastly, errors from CPU architecture, verification environments, interface wrapper and instruction set simulator were found in different verification environment and fixed. To conclude the study, insertion of self-implemented RTL monitor circuit into CPU architecture supply verification information about testbench’s coverage of functional verification.