A Unified System/RTL/FPGA/Chip Verification Methodology for a 3D Graphics SoC
碩士 === 國立中山大學 === 資訊工程學系研究所 === 96 === In recent years, a theme for generally discussion in IC design domain is how to do the efficient verification in complex SoC environment and raise the confidence when chip taped-out. But when we face the different abstraction levels of verification environment...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/kgtcmm |