Memory Allocation of 3D Graphics Data for a 3D Hardware Accelerator

• Main Authors: Hung-Yu Chen, 陳虹宇
• Other Authors: Ing-Jer Huang
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/2nw867

碩士 === 國立中山大學 === 資訊工程學系研究所 === 96 === Hardware implementation is one of common solutions for accelerating 3D Graphics Pipelining Application. In this thesis, our purpose is to probe into the effect of 3D graphics system performance, according to the memory allocation of 3D graphics data and bus architecture for 3D graphics system-on-chip. And we also improve performance of whole application system efficiently by existent hardware resource. For getting the purpose, we use system level of simulation to observe and analyze the access of hardware accelerator in system and find out the key for improving performance. In this paper, we use ESL design to aid us for system simulation. Besides simulation time is much faster than RTL, abstract description is easy to implement and analyze. In memory organization, we must understand the relation of access data of 3D hardware with SDRAM, and reallocation memory. So, we divide each data and put them in different banks of SDRAM, scratch memory of system and built-in memory of hardware. Besides we increase the bandwidth of system bus by using multilayer architecture in system bus, we modify software to up the access times for improving performance. The experiment results point out that we speed up performance for 1.62 times.