| Summary: | 碩士 === 國立東華大學 === 電機工程學系 === 96 === H.264 is a new international video coding standard. Many novel techniques are adopted in motion estimation of H.264. It basically includes the motion vector at quarter pixel resolution with variable block sizes and multiple reference frames. With these attractive characteristics, it can achieve more accurate prediction and higher compression efficiency. However, because of these characteristics, the complexity and computation load of motion estimation increase greatly in H.264.
This thesis proposes a parallel architecture design for motion estimation (ME) by using the new three step search (NTSS) block-matching algorithm. The proposed NTSS-based parallel architecture adopts the partition technique to separate the encoded frame into two parts for operating. By using the partition technique, the search time of the proposed NTSS-based parallel architecture can be reduced more than 1/2 times. In other words, the proposed NTSS-base parallel architecture design produces efficient solution for real-time ME required in video application with high speed requirement. Experimental results show that the proposed architecture is the best tradeoff in terms of hardware area overhead and speed among the all-existing previous works. Also, the proposed architecture design can be used for various video applications from low bit-rate video to HDTV system.
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