| Summary: | 碩士 === 國立東華大學 === 電子工程研究所 === 96 === In this thesis, we try to deal with one of the challenges for the sequential logic design with injection of soft errors. We propose an effective solution to correct the soft error in the transmission stage and latches. In the traditional latch structure, we can’t correct the soft error from internal or external nodes. If we want to fix the system injury that the soft error causes, we need to have the built-in self error resilience (BISER) circuit. By embedding the circuit in our sequential logic circuit, we can reduce the wasting on the soft error correcting circuit area, power efficiency, and performance loss.
We have designed the element mainly used to solve the transmission delay on the short-term mistake. The previous studies have proposed the structure to tolerate the error effect from the internal nodes, but the actual system fault does not necessarily occur in the internal nodes of the structure. In the general structure, BISER designs can have perfect resistance of the error in the input source or transmission path which are not the internal nodes of the designs.
In order to solve the problem, we propose the DSEC structure. The DSEC structure can correct the error of the inner nodes, and keep working for the data transmission. At the same time, the structure can also solve the error from the input of transmission path, and protect the value in the latches.
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