| Summary: | 碩士 === 國立彰化師範大學 === 光電科技研究所 === 96 === A novel fabrication process has been developed for making nanometer-scaled current-perpendicular-to-plane (CPP) device through a nanostencil. The template structure consisting of Si3N4-coated silicon substrate / Pt (20) / SiO2 (x) / Ge (15) (thickness in nm and x is varied to be 50,100 and 200, respectively) was first prepared by thermal evaporation and sputtering method. A deep submicron hole was patterned into an electron beam resist spin-coated on the top of the template, followed by a dry etching to transfer the hole pattern to Ge layer. The sample was then dipped into a BOE etchant and the SiO2 underneath the Ge hole was etched out downward and laterally, giving rise to a very good undercutting profile, a hole template was then completed and ready for all sorts of metal films deposition. The controllable nano-devices can be fabricated through smaller hole template which can be achieved by using e-beam lithography and a trick based on the fact that a buffer film growth vertically may narrow down the template hole at the same time, forming a more and more narrow neck during buffer film growth. So, the scale of device can easily be down to sub-100nm in diameter . We have successfully fabricated the nanometer-scaled CPP magnetic multilayer devices and emitter for field emission by using nanostencil mask technique.
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