Chip Design of LNAs for 802.11a and WIMAX/UWB Applications
碩士 === 國立彰化師範大學 === 積體電路設計研究所 === 96 === This thesis presents the design of a 2-11GhZ low noise amplifier (LNA) and a 5.7GHz gain-variable low noise amplifier fabricated in TSMC 0.18μm 1P6M RF/Mixer-signal CMOS process. First, we propose an 2-11GhZ low noise amplifier. This LNA has illustrated fully...
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| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/56883808405604109467 |
| Summary: | 碩士 === 國立彰化師範大學 === 積體電路設計研究所 === 96 === This thesis presents the design of a 2-11GhZ low noise amplifier (LNA) and a 5.7GHz gain-variable low noise amplifier fabricated in TSMC 0.18μm 1P6M RF/Mixer-signal CMOS process. First, we propose an 2-11GhZ low noise amplifier. This LNA has illustrated fully integrated dual-band LNA that can cover 2-11GHz and 3.1-10.6GHz for WiMAX and UWB receiver. By employing the current-reused configuration with a negative feedback, the proposed LNA provided a peak power gain of 12.46 dB and a good input matching under a power dissipation of 7.52 mW. The NF is ranged from 2.36 to 3.97 dB within the bandwidth.
In the second chip design, we adopt a current-reused technique to design an 5.7 GHz CMOS gain-variable low noise amplifier. There are many LNAs using Chebyshev bandpass filter to achieve wide band matching. We use a simple high pass filter for low noise consideration. Smaller noise figure and chip size is simultaneously attained. Simulation results show that LNA has a maximum 20.7dB power gain. The simulated S11 and S22 are all below -10dB and the minimum noise figure is 3.08dB. The total power consumption with output buffer is 17.2mW.
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