| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 96 === Memory core is one key component in system-on-chip (SOC) designs. Also, memory cores usually represent a significant portion of the chip area. Therefore, the yield of memory cores dominates the yield of the chip. Efficient yield-improvement techniques for memory cores thus are essential for improving the yield of the chip. Diagnosis and repair are two major techniques for improving the yields of memory cores. On the other hand, leakage power issue is another challenge for designing nano-scale SOCs. Drowsy static random access memory (SRAM) is one possible candidate of memory core with low-leakage power consumption. Therefore, we propose efficient diagnosis and repair techniques for drowsy SRAMs in this thesis.
First, we propose a March D2 algorithm for distinguishing drowsy faults (DFs) from non-drowsy faults (NDFs). We also propose a March D6 diagnosis algorithm for distinguishing all DFs of drowsy SRAMs. The test complexity of a March D6 algorithm is O((10*log2N+17+9*log2W)*N), where N represents the number of words of the memory under test; W represents the word width of memory. Second, an efficient built-in self-repair (BISR) scheme is proposed to repair defective drowsy SRAMs. A new redundancy analysis (RA) algorithm is proposed to allocate redundancies of the drowsy SRAM with spare rows, spare columns, and drowsy-masking registers (DMRs) [2]. The proposed BISR scheme can repair DFs by disabling the drowsy operation mode of the corresponding rows with DMRs. Simulation results show that the repair rate (the ratio of the number of repaired memories to the number of defective memories) of the proposed RA algorithm is 91%, which is better than that of repair-most algorithm which offers 67% repair rate.
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