A Boundary-less Design Centering Approach Using Statistical Yield Analysis Results for PLL Circuits

A Boundary-less Design Centering Approach Using Statistical Yield Analysis Results for PLL Circuits

碩士 === 國立中央大學 === 電機工程研究所 === 96 === With the shrinking device size in deep submicron process, the process variation influence on circuit performance is more and more serious, especially for analog circuits. Therefore, design-for-manufacturability (DFM) and design-for-yield (DFY) techniques have bec...

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Bibliographic Details
Main Authors:	I-CHING TSAI, 蔡宜青
Other Authors:	Chien-Nan Jimmy Liu
Format:	Others
Language:	zh-TW
Published:	2008
Online Access:	http://ndltd.ncl.edu.tw/handle/h62r73

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