A Boundary-less Design Centering Approach Using Statistical Yield Analysis Results for PLL Circuits
碩士 === 國立中央大學 === 電機工程研究所 === 96 === With the shrinking device size in deep submicron process, the process variation influence on circuit performance is more and more serious, especially for analog circuits. Therefore, design-for-manufacturability (DFM) and design-for-yield (DFY) techniques have bec...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/h62r73 |